The present invention relates to the field of memory devices. More particularly, the invention relates to a method and arrangement for power saving for a burst mode implementation during reading data from a memory device.
The overall array architecture for a typical integrated circuit containing a memory includes a core memory, herein referred to as a core, and input/output circuitry, herein referred to as the periphery. The core generally contains a plurality of core cells (i.e. individual memory elements) that are arranged in an array of rows and columns. The core cells store at least one bit of data and are accessed through the periphery to external elements, such as a microprocessor, which require the data.
When the core is accessed, the microprocessor or other external element requests data stored in the core. Power is consumed both reading the data from the core to the periphery and driving the data onto the bus connecting the periphery and microprocessor. In general, there is a constant need to decrease the amount of power consumed while providing more powerful and faster elements and circuitry. Either decreasing the power used by individual components or minimizing the power used by the entire access process decreases the power used in retrieving sets of data from the core (either individual sets of bits, words or bytes, depending on the arrangement) and driving the sets of data along the bus to be read by a microprocessor or other external elements.
It is desirable to produce arrangements in which the power consumption is reduced. For example, large amounts of power are consumed when driving retrieved data along the bus dependent on the dynamical changes between successive sets of data being driven. This is to say that, power is consumed when data occupying a position on the bus (say data 0 occupying position 1) and being driven along the bus during one clock cycle changes states (say data 1 occupying position 1) and is driven along the bus during the next clock cycle. If the data occupying a particular position on the bus does not change from one clock cycle to the next clock cycle, significantly less power is consumed.
Thus, it is advantageous to produce an arrangement in which the power consumption is reduced when driving successive sets of data to the bus, thereby increasing battery lifetime in portable computers, for example.
In view of the above, an advantage of the present invention is to reduce the amount of power used in driving sets of data along the bus, particularly during modes when data is xe2x80x9cburst outxe2x80x9d from the memory at high speed. An embodiment of the present invention is a power saving method during burst mode reading of data from a memory device in which data is presently selected from a core memory. The method includes determining whether majority of the presently introduced data has changed from previously introduced data from the core memory. The present data is subjected to an exclusive or logic function (XOR) with the majority determination and this data as well as the majority determination are driven separately to external elements requesting the present data.
Another embodiment of the present invention is a power saving arrangement during burst mode reading of data from a memory device in which a core memory contains selectable data. A determining mechanism determines whether the majority of data presently selected from the core cell has changed from previously selected data from the core memory. A plurality of first XOR gates subject the present data to an exclusive-or logic function with the majority determination. A plurality of drivers separately drive both this data and the majority determination. In this manner power is saved, as the state of the majority of the data being driven from one data set to the next remains unchanged.
The following figures and detailed description of the preferred embodiments will more clearly demonstrate these and other objects and advantages of the invention.